BCM4354 Data Sheet
SDIO Timing
Table 51: SDIO Bus Timinga Parameters (Default Mode)
Symbol Minimum Typical
Parameter
Maximum Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
0
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock low time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL 40pF load on CMD and Data.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 168
BROADCOM CONFIDENTIAL
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