BCM4354 Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 1
Figure 2: BCM4354 Block Diagram ................................................................................................................. 18
Figure 3: Typical Power Topology for the BCM4354 ....................................................................................... 23
Figure 4: Recommended Oscillator Configuration ........................................................................................... 27
Figure 5: Recommended Circuit to Use with an External Reference Clock..................................................... 28
Figure 6: Startup Signaling Sequence ............................................................................................................. 38
Figure 7: CVSD Decoder Output Waveform Without PLC............................................................................... 40
Figure 8: CVSD Decoder Output Waveform After Applying PLC..................................................................... 40
Figure 9: Functional Multiplex Data Diagram................................................................................................... 46
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 47
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 48
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 49
Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 50
Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)......................................................... 51
Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 52
Figure 16: USB Compounded Device Configuration ....................................................................................... 53
Figure 17: USB Full-Speed Timing .................................................................................................................. 55
Figure 18: UART Timing .................................................................................................................................. 57
Figure 19: I2S Transmitter Timing.................................................................................................................... 60
Figure 20: I2S Receiver Timing........................................................................................................................ 60
Figure 21: Example Blend/Switch Usage......................................................................................................... 63
Figure 22: Example Blend/Switch Separation.................................................................................................. 64
Figure 23: Example Soft Mute Characteristic .................................................................................................. 64
Figure 24: Broadcom GCI Mode LTE Coexistence Interface........................................................................... 67
Figure 25: Legacy 3-Wire LTE Coexistence Interface ..................................................................................... 67
Figure 26: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 70
Figure 27: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 70
Figure 28: HSIC Device Block Diagram........................................................................................................... 71
Figure 29: PCI Express Layer Model............................................................................................................... 72
Figure 30: WLAN MAC Architecture ................................................................................................................ 75
Figure 31: WLAN PHY Block Diagram............................................................................................................. 80
Figure 32: Radio Functional Block Diagram (core 0)....................................................................................... 82
Figure 33: WLBGA Ball Map, 4.87 mm × 7.67 mm Array, 192-Ball, A1–V6 (Bottom View—Balls Facing Up)84
Figure 34: WLBGA Ball Map, 4.87 × 7.67 Array, 192-Ball, A7 – V12 (Bottom View—Balls Facing Up) ......... 85
Figure 35: RF Port Location for Bluetooth Testing......................................................................................... 129
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 12
BROADCOM CONFIDENTIAL
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