BCM43455 Preliminary Data Sheet
Ball Map and Pin Descriptions
Section 13: Ball Map and Pin Descriptions
Ball Map
Figure 31: 140-Ball WLBGA Map—Bottom View (Balls Facing Up)
11
10
9
8
7
6
5
4
3
2
1
SDIO_DAT LDO_VDDB
LDO_VDD1 SR_VDDBA
A
B
C
D
E
F
PCIE_TDN PCIE_RDN PCIE_RDP SDIO_CLK
PCIE_RXT
VOUT_3P3
SR_PVSS
A
B
C
D
E
F
A_3
AT5V
P5
T5V
PCIE_REF
CLKP
PCIE_CLK SDIO_DAT SDIO_DAT VOUT_BTL VOUT_LNL VOUT_CLD VOUT_PCI
PCIE_TDP X_AVDD1P
2
SR_VLX
REQ_L
A_1
A_2
DO2P5
DO
O
ELDO
PCIE_REF PCIE_PLL_
SDIO_DAT
A_0
WL_REG_ BT_REG_O
PCIE_VSS
NC1
VDDC
SDIO_CMD
VSSC
PMU_AVSS GPIO_0
CLKN
AVDD1P2
GPIO_14
ON
N
PCI_PME_
L
GPIO_13
PERST_L
NC3
VDDIO_SD
VDDIO
JTAG_SEL
VSSC
GPIO_2
GPIO_1
GPIO_3
VDDC
GPIO_6
GPIO_7
LPO_IN
AVSS_BBP AVDD_BBP
RF_SWCT
RL_8
NC2
VDDIO_RF
GPIO_4
GPIO_9
BT_VDDO
NC
GPIO_5
LL
LL
RF_SW_CT RF_SW_CT
RL_0 RL_1
RF_SWCT RF_SWCT
RL_4 RL_7
VSSC
VDDC
GPIO_10 BT_VDDC
WRF_XTAL WRF_XTAL RF_SW_CT RF_SW_CT RF_SWCT RF_SWCT
BT_PCM_S
VSSC
BT_PCM_I
N
G
H
J
GPIO_8
G
H
J
_XON
_GND1P2
RL_2
RL_3
RL_5
RL_6
YNC
WRF_SYN
TH_VDD3P
3
WRF_XTAL WRF_XTAL WRF_XTAL
BT_GPIO_ BT_GPIO_
BT_PCM_O
BT_I2S_DO
UT
BT_PCM_C
LK
_XOP
_VDD1P35 _VDD1P2
3
4
WRF_SYN
WRF_PMU
_VDD1P35
WRF_SYN WRF_VCO BT_GPIO_ BT_UART_
BT_I2S_W
BT_I2S_DI
S
BT_I2S_CL
K
TH_VDD1P
2
VDDC
BT_VDDC
TH_GND
_GND
2
CTS_N
WRF_RX5 WRF_AFE_ WRF_GEN WRF_EXT_
BT_GPIO_ BT_UART_ BT_UART_ BT_UART_
K
L
GPIO_15
GPIO_16
VSSC
K
L
G_GND
VDD1P35 ERAL_GND
TSSIA
5
RTS_N
TXD
RXD
WRF_GEN
ERAL2_GN
D
WRF_RFIN
_5G
WRF_AFE_ WRF_GPAI BT_LNAVD
BT_PLLVS BT_CLK_R BT_HOST_
BT_IFVSS
BT_PAVSS
VSSC
BT_VDDC
GND
O_OUT
D1P2
S
EQ
WAKE
WRF_PAO WRF_PA_ WRF_TXMI WRF_RX2 BT_LNAVS
BT_PLLVD FM_PLLVS
FM_PLLVD BT_DEV_W
M
N
FM_RFVSS
M
N
UT_5G
GND3P3
X_VDD
G_GND
S
D1P2
S
D1P2
AKE
WRF_PA_V
DD3P3
WRF_PAO WRF_RFIN
BT_PAVDD BT_IFVDD1
FM_RFVDD
1P2
BT_RF
FM_RFIN
FM_AOUT2 FM_AOUT1
UT_2G
_2G
2P5
P2
11
10
9
8
7
6
5
4
3
2
1
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 80
BROADCOM CONFIDENTIAL
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