BCM43455 Preliminary Data Sheet
PCM Interface
Short Frame Sync, Slave Mode
Figure 12: PCM Timing Diagram (Short Frame Sync, Slave Mode)
1
2
3
PCM_BCLK
4
5
PCM_SYNC
PCM_OUT
9
HIGH IMPEDANCE
6
8
7
PCM_IN
Table 7: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)
Reference Characteristics Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
9
PCM bit clock frequency
–
–
–
–
–
–
–
–
–
–
12
–
MHz
ns
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
41
41
8
–
ns
–
ns
8
–
ns
0
25
–
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
0
25
ns
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 51
BROADCOM CONFIDENTIAL
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