BCM43455 Preliminary Data Sheet
Microprocessor and Memory Unit for Bluetooth
Section 6: Microprocessor and Memory
Unit for Bluetooth
The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-
RT debug and JTAG interface units. It runs software from the link control (LC) layer, up to the host controller
interface (HCI).
The ARM core is paired with a memory unit that contains 845 KB of ROM memory for program storage and boot
ROM, 270 KB of RAM for data scratchpad and patch RAM code. The internal ROM allows for flexibility during
power-on reset to enable the same device to be used in various configurations. At power-up, the lower-layer
protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features
additions. These patches may be downloaded from the host to the BCM43455 through the UART transports.
The mechanism for downloading via UART is identical to the proven interface of the BCM4329 and BCM4330
devices.
RAM, ROM, and Patch Memory
The BCM43455 Bluetooth core has 270 KB of internal RAM which is mapped between general purpose scratch
pad memory and patch memory and 845 KB of ROM used for the lower-layer protocol stack, test mode software,
and boot ROM. The patch memory capability enables the addition of code changes for purposes of feature
additions and bug fixes to the ROM memory.
Reset
The BCM43455 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The
BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the
POR circuit is held in reset.
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 46
BROADCOM CONFIDENTIAL
CYPRESS [ CYPRESS ]
