BCM43455 Preliminary Data Sheet
SDIO Timing
Data Timing
Figure 42: SDIO Data Timing (DDR50 Mode)
FPP
SDIO_CLK
tISU2x
tIH2x
tISU2x
tIH2x
DAT[3:0]
Invalid
Data
Invalid
Data
Invalid
Data
Invalid
input
tODLY2x (max)
tODLY2x (max)
tODLY2x
(min)
tODLY2x
(min)
Available timing
window for card
output transition
DAT[3:0]
output
Data
Data
Data
Available timing
window for host to
sample data from card
In DDR50 mode, DAT[3:0] lines are sampled on both
edges of the clock (not applicable for CMD line)
Table 60: SDIO Bus Timing Parameters (DDR50 Mode)
Parameter
Input CMD
Symbol
Minimum
Maximum
Unit Comments
Input setup time
Input hold time
tISU
tIH
6
–
–
ns
ns
CCARD < 10 pF (1 Card)
CCARD < 10 pF (1 Card)
0.8
Output CMD
Output delay time
Output hold time
tODLY
tOH
–
13.7
–
ns
ns
CCARD < 30 pF (1 Card)
CCARD < 15 pF (1 Card)
1.5
Input DAT
Input setup time
Input hold time
tISU2x
tIH2x
3
–
–
ns
ns
CCARD < 10 pF (1 Card)
CCARD < 10 pF (1 Card)
0.8
Output DAT
Output delay time
Output hold time
tODLY2x
tODLY2x
–
7.5
–
ns
ns
CCARD < 25 pF (1 Card)
CCARD < 15 pF (1 Card)
1.5
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 147
BROADCOM CONFIDENTIAL
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