BCM43455 Preliminary Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 1
Figure 2: BCM43455 Block Diagram ............................................................................................................... 20
Figure 3: Typical Power Topology (Page 1 of 2).............................................................................................. 24
Figure 4: Typical Power Topology (Page 2 of 2).............................................................................................. 25
Figure 5: Recommended Oscillator Configuration ........................................................................................... 29
Figure 6: Recommended Circuit to Use With an External Reference Clock.................................................... 30
Figure 7: Startup Signaling Sequence Prior to Software Download ................................................................ 42
Figure 8: CVSD Decoder Output Waveform Without PLC............................................................................... 44
Figure 9: CVSD Decoder Output Waveform After Applying PLC..................................................................... 44
Figure 10: Functional Multiplex Data Diagram................................................................................................. 49
Figure 11: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 50
Figure 12: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 51
Figure 13: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 52
Figure 14: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 53
Figure 15: PCM Burst Mode Timing (Receive Only, Short Frame Sync)......................................................... 54
Figure 16: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 55
Figure 17: UART Timing .................................................................................................................................. 57
Figure 18: I2S Transmitter Timing.................................................................................................................... 59
Figure 19: I2S Receiver Timing........................................................................................................................ 59
Figure 20: Audio SNR for Blend, Switch, and FME Modes.............................................................................. 62
Figure 21: Stereo Separation for Blend, Switch, and FME Modes .................................................................. 63
Figure 22: Example Soft Mute Characteristic .................................................................................................. 63
Figure 23: Broadcom GCI or BT-SIG WCI-2 LTE Coexistence Interface ........................................................ 66
Figure 24: 3-Wire LTE Coexistence Interface.................................................................................................. 66
Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 69
Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 69
Figure 27: PCI Express Layer Model............................................................................................................... 70
Figure 28: WLAN MAC Architecture ................................................................................................................ 73
Figure 29: WLAN PHY Block Diagram............................................................................................................. 77
Figure 30: Radio Functional Block Diagram .................................................................................................... 79
Figure 31: 140-Ball WLBGA Map—Bottom View (Balls Facing Up) ............................................................... 80
Figure 32: Port Locations for Bluetooth Testing............................................................................................. 100
Figure 33: Port Locations for WLAN Testing ................................................................................................. 112
Figure 34: SDIO Bus Timing (Default Mode) ................................................................................................. 139
Figure 35: SDIO Bus Timing (High-Speed Mode).......................................................................................... 141
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 13
BROADCOM CONFIDENTIAL
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