BCM43455 Preliminary Data Sheet
PCIe LDO
PCIe LDO
Table 49: PCIe LDO Specifications
Specification
Notes
Min. V = V + 0.15V = 1.35V (where
Min.
Typ.
Max. Units
Input supply voltage, Vin
1.3
1.35
1.5
V
IN
O
V = 1.2V)dropout voltage requirement
O
must be met under maximum load.
Output Current
Peak load=80 mA. Average load=35 mA
0.1
1.1
–
55
mA
V
Output Voltage, V
Programmable in 25 mV steps.
Default = 1.2V
1.2
1.275
o
Dropout Voltage
At maximum load
–
–
150
+4
12
mV
%
Output Voltage DC Accuracy Includes line/load regulation
–4
–
–
Quiescent current
No load
10
550
–
μA
55 mA load
–
570
5
μA
Line Regulation
V
from (V + 0.1V) to 1.5V, 150 mA load –
mV/V
IN
O
Load Regulation
Leakage Current
Load from 1 mA to 150 mA
Power-down
–
–
–
–
0.02
5
0.05
20
mV/mA
μA
Bypass mode
0.02
–
1.5
μA
Output Noise
PSRR
@30 kHz, 60–150 mA load C = 2.2 μF
@100 kHz, 60–150 mA load C = 2.2 μF
60
35
nV/rt Hz
nV/rt Hz
o
o
@ 1kHz, Input > 1.35V, C = 2.2 μF,
20
–
–
dB
o
V = 1.2V
o
LDO Turn-on Time
LDO turn-on time when balance of chip is up –
140
180
–
μs
a
External Output Capacitor, C Total ESR (trace/capacitor):
0.47
μF
o
0.27
5 mΩ–240 mΩ
External Input Capacitor
Only use an external input capacitor at the –
VDD_LDO pin if it is not supplied from
CBUCK output.
1
2.2
μF
Total ESR (trace/capacitor): 30 mΩ–200 mΩ
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part
tolerance, DC-bias, temperature, and aging.
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 135
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