CYW4343X
Figure 25. WLAN Boot-Up Sequence
Ramp time from 0V to 4.3V > 40 µs
0.6V
VBAT
VDDIO
> 2 Sleep Clock cycles
WL_REG_ON
< 1.5 ms
< 3 ms
VDDC
(from internal PMU)
Internal POR
After a fixed delay following internal POR going high,
the device responds to host F0 (address 0x14) reads.
< 50 ms
Device requests a reference clock.
1
1
15 ms
After 15 ms the reference clock
is assumed to be up. Access to
PLL registers is possible.
SPI Host Interaction:
Host polls F0 (address 0x14) until it reads
a predefined pattern.
Host sets wake‐up‐wlan bit
1
and waits 15 ms , the
maximum time for
1
After 15 ms, the host
reference clock availability.
programs the PLL registers to
set the crystal frequency.
Chip‐active interrupt is asserted after the PLL locks.
WL_IRQ
Host downloads
code.
1
This wait time is programmable in sleep‐clock increments from 1 to 255 (30 us to 15 ms).
Document No. 002-14797 Rev. *H
Page 33 of 128
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