欢迎访问ic37.com |
会员登录 免费注册
发布采购

BCM43438KUBG 参数 Datasheet PDF下载

BCM43438KUBG图片预览
型号: BCM43438KUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip IEEE 802.11ac b/g/n MAC/Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver]
分类和应用:
文件页数/大小: 101 页 / 1121 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号BCM43438KUBG的Datasheet PDF文件第49页浏览型号BCM43438KUBG的Datasheet PDF文件第50页浏览型号BCM43438KUBG的Datasheet PDF文件第51页浏览型号BCM43438KUBG的Datasheet PDF文件第52页浏览型号BCM43438KUBG的Datasheet PDF文件第54页浏览型号BCM43438KUBG的Datasheet PDF文件第55页浏览型号BCM43438KUBG的Datasheet PDF文件第56页浏览型号BCM43438KUBG的Datasheet PDF文件第57页  
PRELIMINARY  
CYW43438  
12.4 External Coexistence Interface  
The CYW43438 supports a 2-wire coexistence interface to enable signaling between the device and an external colocated wireless  
device in order to manage wireless medium sharing for optimal performance. The external colocated device can be any of the following  
ICs: GPS, WiMAX, LTE, or UWB. An LTE IC is used in this section for illustration.  
Figure 31 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure:  
GPIO_1: WLAN_SECI_TX output to an LTE IC.  
GPIO_2: WLAN_SECI_RX input from an LTE IC.  
Figure 31. 2-Wire Coexistence Interface to an LTE IC  
GPIO_1  
GPIO_2  
WLAN_SECI_TX  
WLAN_SECI_RX  
UART_IN  
WLAN  
BT/FM  
UART_OUT  
Coexistence  
Interface  
CYW43438  
LTE/IC  
Notes:  
OR’ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by  
setting the GPIO mask registers appropriately.  
WLAN_SECI_OUT and WLAN_SECI_IN are multiplexed on the GPIOs.  
See Figure 27 and Table 14: “UART Timing Specifications” for UART timing.  
12.5 JTAG Interface  
The CYW43438 supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB  
assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary  
debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins  
by means of test points or a header on all PCB designs.  
12.6 UART Interface  
One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI  
pin, and UART_TX is available on the JTAG_TDO pin.  
The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the  
CYW43438 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It  
is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.  
Document Number: 002-14796 Rev. *K  
Page 53 of 101  
 复制成功!