BCM4339 Preliminary Data Sheet
Generic SPI Mode
Table 18: gSPI Registers (Cont.)
Bit Access Default Description
Address Register
x0002
Status enable
0
1
2
R/W
R/W
R/W
1
0
0
0: no status sent to host after read/write
1: status sent to host after read/write
0: do not interrupt if status is sent
1: interrupt host even if status is sent
0: response delay applicable to F1 read only
1: response delay applicable to all function read
–
Interrupt with status
Response delay for
all
x0003
x0004
Reserved
–
0
–
–
0
Interrupt register
R/W
Requested data not available; Cleared by writing a
1 to this location
1
2
5
6
7
5
6
7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
F2/F3 FIFO underflow due to last read
F2/F3 FIFO overflow due to last write
F2 packet available
F3 packet available
F1 overflow due to last write
F1 Interrupt
x0005
Interrupt register
F2 Interrupt
F3 Interrupt
x0006–
x0007
Interrupt enable
register
15:0 R/W/U 16'hE0E7 Particular Interrupt is enabled if a corresponding bit
is set
x0008–
x000B
Status register
31:0 R
32'h0000 Same as status bit definitions
x000C– F1 info register
x000D
0
1
R
R
1
F1 enabled
0
F1 ready for data transfer
F1 max packet size
F2 enabled
13:2 R/U
12'h40
x000E– F2 info register
x000F
0
1
R/U
R
1
0
F2 ready for data transfer
15:2 R/U
14'h800 F2 max packet size
x0010–
x0011
F3 info register
0
1
R/U
R
1
0
F3 enabled
F3 ready for data transfer
15:2 R/U
31:0 R
14'h800 F3 max packet size
x0014–
x0017
Test–Read only
register
32'hFEE This register contains a predefined pattern, which
DBEAD the host can read and determine if the gSPI
interface is working properly.
x0018–
x001B
Test–R/W register
31:0 R/W/U 32'h0000 This is a dummy register where the host can write
0000
some pattern and read it back to determine if the
gSPI interface is working properly.
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 81
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