BCM4339 Preliminary Data Sheet
Sequencing of Reset and Regulator Control Signals
Figure 55: WLAN = ON, Bluetooth = OFF
32.678 kHz
Sleep Clock
90% of VH
VBAT*
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
Figure 56: WLAN = OFF, Bluetooth = ON
32.678 kHz
Sleep Clock
90% of VH
VBAT*
VDDIO
~ 2 Sleep cycles
WL_REG_ON
BT_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.
2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 174
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