BCM4339 Preliminary Data Sheet
SDIO/gSPI Timing
gSPI Signal Timing
The gSPI host and device always use the rising edge of clock to sample data.
Figure 52: gSPI Timing
Table 60: gSPI Timing Parameters
Parameter
Symbol Minimum
Maximum
Units Note
ns Fmax = 48 MHz
Clock period
T1
20.8
–
Clock high/low
Clock rise/fall timea
T2/T3
T4/T5
(0.45 × T1) – T4 (0.55 × T1) – T4 ns
–
–
2.5
ns
ns
ns
ns
ns
Measured from 10% to 90% of
VDDIO
Input setup time
Input hold time
T6
T7
5.0
5.0
5.0
5.0
–
Setup time, SIMO valid to
SPI_CLK active edge
–
Hold time, SPI_CLK active edge
to SIMO invalid
Output setup time T8
–
Setup time, SOMI valid before
SPI_CLK rising
Output hold time
T9
–
Hold time, SPI_CLK active edge
to SOMI invalid
CSX to clockb
Clock to CSXa
–
–
7.86
–
–
–
ns
ns
CSX fall to 1st rising edge
Last falling edge to CSX high
a. Limit applies when SPI_CLK = Fmax. For slower clock speeds, longer rise/fall times are acceptable provided that
the transitions are monotonic and the setup and hold time limits are complied with.
b. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multiple-
word transaction).
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 168
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