BCM4339 Preliminary Data Sheet
WLAN GPIO Signals and Strapping Options
WLAN GPIO Signals and Strapping Options
The pins listed in Table 21 are sampled at power-on reset (POR) to determine the various operating modes.
Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR,
each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping
option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change
the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kꢀ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 21: WLAN GPIO Functions and Strapping Options
FCBGA
Pin #
WLBGA
Pin #
WLCSP
Pin #
Default
Function
Pin Name
Description
SDIO_SELa
GPIO_7
B7
D4
196
1
GPIO_8
E8
H1
–
197
202
171
0
0
1
SDIO_PADVDDIO
PCIE_DISABLE
GPIO_14
SDIO_CLK
A3
CPU-LESS/SPROM_DISABLEa
SPI_SELa
B11
B11
SDIO_DATA_2
C9
D10
175
1
a. See Table 22, Table 23, and Table 24.
Table 22: SDIO/gSPI I/O Voltage Selection (All Packages)
SDIO_SEL
SPI_SEL
SDIO_PADVDDIO
Mode
1
1
0
0
0
X
X
1
1
0
0
1
0
1
X
1.8V I/O
3.3V I/O
1.8V I/O
3.3V I/O
3.3V I/O
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 114
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