PRELIMINARY
CYW43364
2.5 Power-Off Shutdown
The CYW43364 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW43364 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW43364 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43364, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43364 to be fully integrated in an embedded device and
to take full advantage of the lowest power-savings modes.
When the CYW43364 is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW43364 has two signals (see Table 2) that enable or disable the WLAN circuits and the internal regulator blocks, allowing the
host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 14.:
“Power-Up Sequence and Timing,” on page 62.
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal
Description
This signal is used by the PMU to power-up the WLAN section. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. This pin has an
internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming.
WL_REG_ON
Document Number: 002-14781 Rev. *C
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