BCM4334W Advance Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram....................................................................................................................1
Figure 1: BCM4334W Block Diagram .................................................................................................................1
Figure 2: Mobile Phone System Block Diagram..................................................................................................4
Figure 3: Typical Power Topology.......................................................................................................................6
Figure 4: Recommended Oscillator Configuration ...........................................................................................10
Figure 5: Recommended Circuit to Use with an External Dedicated TCXO......................................................11
Figure 6: Recommended Circuit to Use with an External Shared TCXO...........................................................11
Figure 7: Startup Signaling Sequence...............................................................................................................22
Figure 8: CVSD Decoder Output Waveform Without PLC ................................................................................23
Figure 9: CVSD Decoder Output Waveform After Applying PLC ......................................................................24
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode)................................................................30
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)...................................................................31
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode).................................................................32
Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)....................................................................33
Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync) ...........................................................34
Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ............................................................35
Figure 16: UART Timing....................................................................................................................................37
2
Figure 17: I S Transmitter Timing.....................................................................................................................39
2
Figure 18: I S Receiver Timing..........................................................................................................................40
Figure 19: Signal Connections to SDIO Host (SD 4-Bit Mode) ..........................................................................44
Figure 20: Signal Connections to SDIO Host (SD 1-Bit Mode) ..........................................................................44
Figure 21: Signal Connections to SDIO Host (gSPI Mode) ................................................................................45
Figure 22: gSPI Write Protocol .........................................................................................................................45
Figure 23: gSPI Read Protocol ..........................................................................................................................46
Figure 24: gSPI Command Structure.................................................................................................................46
Figure 25: gSPI Signal Timing Without Status (32-bit big endian shown).........................................................47
Figure 26: gSPI Signal Timing with Status (Response Delay = 0) (32-bit big endian shown) ............................48
Figure 27: WLAN Boot-Up Sequence................................................................................................................51
Figure 28: WLAN MAC Architecture.................................................................................................................53
Figure 29: WLAN PHY Block Diagram ...............................................................................................................57
Figure 30: STBC Implementation in the Receive Path......................................................................................57
Figure 31: 109-WLBGA Ball Map (Bottom View)..............................................................................................59
Figure 32: 208-WLCSP Bump Map (Bottom View) ...........................................................................................60
Figure 33: RF Port Location for Bluetooth Testing ...........................................................................................86
Figure 34: Port Locations..................................................................................................................................93
BROADCOM
®
April 30, 2014 • 4334W-DS103-R
Page 1
BROADCOM CONFIDENTIAL
CYPRESS [ CYPRESS ]
