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BCM4330FKUBG 参数 Datasheet PDF下载

BCM4330FKUBG图片预览
型号: BCM4330FKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PBGA133, WLBGA-133]
分类和应用:
文件页数/大小: 168 页 / 1861 K
品牌: CYPRESS [ CYPRESS ]
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2
BCM4330 Preliminary Data Sheet  
I S Interface  
2
I S Interface  
The BCM4330 supports two independent I2S digital audio ports: one for Bluetooth audio, and one for high-  
fidelity FM audio. The I2S interface for FM audio supports both master and slave modes. The I2S signals are:  
• I2S clock: I2S SCK  
• I2S Word Select: I2S WS  
• I2S Data Out: I2S SDO  
• I2S Data In: I2S SDI  
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an  
output. I2S data input is used for FM Tx. The channel word length is 16 bits and the data is justified so that the  
MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each  
data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit  
clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS  
is high. Data bits sent by the BCM4330 are synchronized with the falling edge of I2S_SCK and should be sampled  
by the receiver on the rising edge of I2S_SSCK.  
The clock rate in master mode is either of the following:  
48 kHz x 32 bits per frame = 1.536 MHz  
48 kHz x 50 bits per frame = 2.400 MHz  
The master clock is generated from the input reference clock using a N/M clock divider.  
In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.  
I2S Timing  
Note: Timing values specified in Table 13 are relative to high and low threshold levels.  
®
BROADCOM  
BCM4330 Preliminary Data Sheet  
April 28, 2011 • 4330-DS304-RI  
Page 63  
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