BCM4330 Preliminary Data Sheet
Microprocessor and Memory Unit for Bluetooth
Section 7: Microprocessor and Memory Unit for
Bluetooth
The Bluetooth microprocessor core is based on the ARM® Cortex™-M3 32-bit RISC processor with embedded
ICE-RT debug and JTAG interface units. It runs software from the link control (LC) layer, up to the host controller
interface (HCI).
The ARM core is paired with a memory unit that contains 560 KB of ROM memory for program storage and
boot ROM, 152 KB of RAM for data scratchpad and patch RAM code. The internal ROM allows for flexibility
during power-on reset to enable the same device to be used in various configurations. At power-up, the lower-
layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features
additions. These patches may be downloaded from the host to the BCM4330 through the UART transports. The
mechanism for downloading via UART is identical to the proven interface of the BCM4329 device.
RAM, ROM, and Patch Memory
The BCM4330 Bluetooth core has 152 KB of internal RAM which is mapped between general purpose scratch
pad memory and patch memory and 560 KB of ROM used for the lower-layer protocol stack, test mode
software, and boot ROM. The patch memory capability enables the addition of code changes for purposes of
feature additions and bug fixes to the ROM memory.
Reset
The BCM4330 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The
reset can also be driven by an active-low, external reset signal, BT_RST_N, that can be used to externally control
the device, forcing it into a power-on reset state. (Note that the BT_RST_N signal is independent of the POR
reset.)
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BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 52
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