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BCM4330FKUBG 参数 Datasheet PDF下载

BCM4330FKUBG图片预览
型号: BCM4330FKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PBGA133, WLBGA-133]
分类和应用:
文件页数/大小: 168 页 / 1861 K
品牌: CYPRESS [ CYPRESS ]
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BCM4330 Preliminary Data Sheet  
TCXO  
Table 2: Crystal Oscillator and External Clock – Requirements and Performance (Cont.)  
External Frequency  
Referenceb c  
Crystala  
Min Typ  
Parameter  
Conditions/Notes  
Max Min Typ  
Max Units  
–128 dBc/Hz  
Phase Noisef  
37.4 MHz clock at 1 kHz offset  
(802.11n, 5 GHz)  
37.4 MHz clock at 10 kHz offset –  
37.4 MHz clock at 100 kHz offset –  
37.4 MHz clock at 1 MHz offset –  
–138 dBc/Hz  
–143 dBc/Hz  
–148 dBc/Hz  
a. (Crystal) Use WRF_XTAL_OP and WRF_XTAL_ON, internal power to pin WRF_XTAL_VDD1P2.  
b. (TCXO) See “TCXO” on page 33 for alternative connection methods.  
c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the  
reference clock frequency in MHz.  
d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high.  
Note that 52 MHz is not an auto-detected frequency using the LPO clock.  
e. The frequency step size is approximately 80 Hz resolution.  
f. If the selected clock has a flat phase noise response above 100 kHz, that is, the phase noise at and above  
100 kHz is constant, then subtract 1dB from all 1 kHz, 10 kHz, and 100 kHz values shown. For example, for the  
2.4 GHz 802.11b/g values, the phase noise requirements change from –115, –125, and –130 dBc/Hz to  
–116, –126, and –131 dBc/Hz respectively. Ignore the 1 MHz requirements when the phase noise is flat  
above 100 kHz.  
®
BROADCOM  
BCM4330 Preliminary Data Sheet  
April 28, 2011 • 4330-DS304-RI  
Page 35  
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