BCM4330 Preliminary Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram....................................................................................................................2
Figure 2: BCM4330 Block Diagram...................................................................................................................21
Figure 3: Mobile Phone Block System Diagram................................................................................................25
Figure 4: Typical Power Topology.....................................................................................................................27
Figure 5: Recommended Oscillator Configuration ...........................................................................................32
Figure 6: Recommended Circuit to Use with an External Dedicated TCXO......................................................33
Figure 7: Recommended Circuit to Use with an External Shared TCXO...........................................................33
Figure 8: Startup Signaling Sequence...............................................................................................................46
Figure 9: CVSD Decoder Output Waveform Without PLC ................................................................................48
Figure 10: CVSD Decoder Output Waveform After Applying PLC ....................................................................48
Figure 11: Functional Multiplex Data Diagram.................................................................................................54
Figure 12: PCM Timing Diagram (Short Frame Sync, Master Mode)................................................................55
Figure 13: PCM Timing Diagram (Short Frame Sync, Slave Mode)...................................................................56
Figure 14: PCM Timing Diagram (Long Frame Sync, Master Mode).................................................................57
Figure 15: PCM Timing Diagram (Long Frame Sync, Slave Mode)....................................................................58
Figure 16: PCM Burst Mode Timing (Receive Only, Short Frame Sync) ...........................................................59
Figure 17: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ............................................................60
Figure 18: UART Timing....................................................................................................................................62
Figure 19: I2S Transmitter Timing.....................................................................................................................65
Figure 20: I2S Receiver Timing..........................................................................................................................65
Figure 21: Example Blend/Switch Usage..........................................................................................................69
Figure 22: Example Blend/Switch Separation ..................................................................................................69
Figure 23: Example Soft Mute Characteristic...................................................................................................70
Figure 24: Signal Connections to SDIO Host (SD 4-Bit Mode) ..........................................................................75
Figure 25: Signal Connections to SDIO Host (SD 1-Bit Mode) ..........................................................................75
Figure 26: Signal Connections to SDIO Host (gSPI Mode) ................................................................................76
Figure 27: gSPI Write Protocol .........................................................................................................................77
Figure 28: gSPI Read Protocol ..........................................................................................................................77
Figure 29: gSPI Command Structure.................................................................................................................78
Figure 30: gSPI Signal Timing Without Status...................................................................................................79
Figure 31: gSPI Signal Timing with Status (Response Delay = 0) ......................................................................80
Figure 32: WLAN Boot-Up Sequence................................................................................................................83
Figure 33: HSIC Device Block Diagram..............................................................................................................84
Figure 34: WLAN MAC Architecture.................................................................................................................86
Figure 35: WLAN PHY Block Diagram ...............................................................................................................91
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BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 15
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