CYW20702
5.5 SPI
The CYW20702 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible.
The physical interface between the SPI master and the CYW20702 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI,
and SPI_SO) and one interrupt signal (SPI_INT). The 20702 internal SPI transport signals are multiplexed to the UART pins as fol-
lows: 20702-pin F6 --> UART_TXD (MISO); 20702-pin G7 --> UART_CTS (SPI_CLK); 20702-pin E5 --> UART_RTS (CS); and
20702-pin D7 --> UART_RXD (MOSI). The GPIO_1 is used for the SPI interrupt signal (SPI_INT). The CYW20702 can be config-
ured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or
active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or
big-endian. Additionally, proprietary sleep mode, half-duplex handshaking is implemented between the SPI master and the
CYW20702.
SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload.
The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it
controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols.
Note: The 20702 pins E7, F7, G8, and E8 are used for SPI serial flash access. When the SPI transport detection is used, the serial
flash interface may not be used because SCL must be tied low.
5.6 Simultaneous UART Transport and Bridging
The CYW20702 supports UART or USB interfaces that can function as the host controller interface (HCI). Typically, a customer
application would choose one of the two interfaces and the other would be idle. The CYW20702 allows the UART transport to operate
simultaneously with the USB. To operate this way, the assumption is that the USB would function as the primary host transport, while
the UART would function as a secondary communication channel that can operate at the same time. This can enable the following
applications:
■ Bridging primary HCI transport traffic to another device via the UART
■ Generic communication to an external device for a vendor-supported application via the UART
Simultaneous UART transport and bridging is enabled by including:
■ Two dedicated 64-byte FIFOs, one for the input and one for the output
■ Additional DMA channels
■ Additional vendor-supported commands over the HCI transport
Document Number: 002-14773 Rev. *L
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