BCM4319 Preliminary Data Sheet
Signal Descriptions
Table 6: 138-Ball WLBGA Signal Descriptions (Cont.)
Type Description
Ball
Signal Name
WJ7
WJ8
AMODE_EXT_LNA_PU
AMODE_EXT_LNA_GAIN
O
O
Enable signal for optional external 802.11a LNA.
Control signal for optional external 802.11a LNA.
Integrated LDOs
WN5
VDD_CLDO
I
Input supply pin for CLDO: also functions as the feedback
pin for the CBUCK switching regulator
WN6
WL7
WP5
WP6
WL8
VDD_LNLDO1
VDD_LNLDO2
VOUT_CLDO
I
Input supply pin for LNLDO1
I
Input supply pin for LNLDO2 (backup linear regulator)
1.2V output for core LDO, 200 mA
O
O
O
VOUT_LNLDO1
VOUT_LNLDO2
1.2V output for low noise LNLDO1, 150 mA
1.2V or 2.5V–3.1V programmable output for low noise
LNLDO2, 50 mA
WM6
WP9
VREF_LDO
O
O
Vref bypass: Connect external decoupling capacitor to
ground.
SR_AVDD2P5
2.5V LDO2p5 output: used for various internal BCM4319
blocks in addition to the USB PHY: the output capacitor is
required even when USB functionality is not used.
WN7
WP7
WM7
WL9
SR_PALDO
O
O
O
O
I
Internal PALDO output or feedback of output from external
PNP
SR_PALDO
SR_PNPO
Control output for PNP base
Test output for switcher/LDOs
Battery supply input for PALDO
SR_TESTSWG
SR_VDDBAT3
SR_VDDBAT3
SR_VDDNLDO
WN8
WP8
WP10
I
O
NLDO reference pin output: Connect to 220 nF external
capacitor to ground. Do not use for other external circuits.
Integrated Switching Regulator
WL10
WL11
WN9
SR_VDDBAT1
SR_VDDBAT1
SR_VDDBAT2
SR_VLX1
I
I
Core buck regulator: Battery voltage input
I
WM11
WN11
WP11
O
O
I
Core buck regulator: Output to inductor
–
SR_VLX1
SR_VSSPLDO
Tracks battery voltage: Connect to 220 nF external
capacitor to battery.
SDIO Bus Interface* (IO supply = VDDIO_SD)
WE11
WJ11
WH11
WG11
WF8
SDIO_CMD
I/O SDIO command line
I/O SDIO data line 0
I/O SDIO data line 1
I/O SDIO data line 2
I/O SDIO data line 3
I/O SDIO clock
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CLK
WK11
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 50
April 2, 2014 • 4319-DS05-R
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