BCM4319 Preliminary Data Sheet
PMU Sequencer
Figure 4: Power Topology Example
BCM4319
BCM4319
VBAT 2.7V - 5.5V
VDDIO 1.8 to 3.3V
LN LD01
WL Radio
RF PLL
Input: 1.4V
1.2V
Output:1.2V 150 mA
WL AFE
(Optional)
LN LD02
Xtal
BCM4319
Input: 1.4 or 3.3V
Output: 1.2 or 2.5-3.1V, 50 mA
VDDIO and VDDIO_SD
Core Logic Blocks
WL Radio
(noise insensitive)
CLDO
Core Buck Regulator
1.4V
Input: 1.4V
1.2V
(300 mA)
Output:1.2V 200 mA
WL Digital
USB
LDO2p5
2.5V 50 mA
USB 2.0 Phy, other
internal blocks
VDDIO_RF
WL OTP
PALDO
(3.3V, 400 mA)
Internal WLAN
Power Amplifier
USBPHY 3.3V
NOTE: Shaded areas are internal to the BCM4319.
AFE: Analog front end
OTP: One-time programmable memory
PLL: Phase-locked loop
WL: Wireless LAN
PMU Sequencer
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various
system resources based on a computation of the required resources and the relationship between resources
and their enable and disable times.
In each device state, a minimum set of resources is always available, as defined in the PMU control registers.
Additional resources can be enabled on request from various sources, including clock requests from cores and
timers in any of the active resources. The PMU sequencer maps clock requests into a set of resources required
to produce the requested clocks.
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 18
April 2, 2014 • 4319-DS05-R
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