CYW20734
1.5 PCM Interface
The CYW20734 includes a PCM interface that shares pins with the I2S interface. The PCM Interface on the CYW20734 can connect
to linear PCM codec devices in master or slave mode. In master mode, the CYW20734 generates the PCM_CLK and PCM_SYNC
signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW20734.
The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.
1.5.1 Slot Mapping
The CYW20734 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample
interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or
1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow
other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM
clock during the last bit of the slot.
1.5.2 Frame Synchronization
The CYW20734 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization
mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
1.5.3 Data Formatting
The CYW20734 may be configured to generate and accept several different data formats. For conventional narrowband speech mode,
the CYW20734 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various
data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a
programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
1.5.4 Burst PCM Mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and
save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with
an HCI command from the host.
1.6 Clock Frequencies
The CYW20734 uses a 24 MHz crystal oscillator (XTAL).
1.6.1 Crystal Oscillator
The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load capacitors in the range of
5 pF to 30 pF are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see Figure 3).
Figure 3. Recommended Oscillator Configuration—12 pF Load Crystal
22 pF
XIN
Crystal
XOUT
20 pF
Document Number: 002-14874 Rev. *S
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