CYW20732A0
Table 3. CYW20732 First SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MOSI
SPI_MOSI
SPI_MISO
SPI_MISO
SPI_MISO
SPI_CSa
Configured Pin Name
SCL
–
SDA
P24
P26
P32
–
–
–
–
–
–
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 4. CYW20732 Second SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_CSa
Configured Pin Name
P3
–
P0
P1
P25
–
–
–
–
P4
P24
P27
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 5. CYW20732 Second SPI Set (Slave Mode)
Pin Name
SPI_CLK
SPI_CS
Configured Pin Name
P3
–
P0
P27
P33
–
P1
–
P2
–
P24
–
P25
–
P26
P32
1.6 Microprocessor Unit
The CYW20732 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components.
The microprocessor is based on an ARM Cortex-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units.
The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code. The SoC
has a total storage of 380 KB, including RAM and ROM.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with
an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed
from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.6.1 EEPROM Interface
The CYW20732 provides a Cypress Serial Control (CSC) master interface. BSC is programmed by the CPU to generate four types
of bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and fast mode
devices. BSC is compatible with an NXP I2C slave device, except that master arbitration (multiple I2C masters contending for the bus)
is not supported.
The EEPROM can contain customer application configuration information including application code, configuration data, patches,
pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.
Native support for the Microchip 24LC128, Microchip 24AA128, and the STMicroelectronics M24128-BR is included.
1.6.2 Serial Flash Interface
The CYW20732 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Document Number: 002-14837 Rev. *L
Page 7 of 35
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