BCM20730 Data Sheet
Timing and AC Characteristics
SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz
when 2.2V ≥ VDDIO ≥ 1.62V.
Figure 13 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in
Table 19, Table 20 on page 50, Table 21 on page 50, Table 22 on page 51.
Figure 13: SPI Timing Diagram
5
6
CS
SCLK
Mode 1
SCLK
Mode 3
2
4
1
MSB
MSB
LSB
LSB
MOSI
MISO
3
Invalid bit
a
Table 19: SPI1 Timing Values—SCLK = 12 MHz and VDDM = 3.2V
b
Reference Characteristics
Symbol
Min
Typical
Max Unit
1
2
3
4
Output setup time, from MOSI
Tds_mo
–
20
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
data valid to sample edge of SCLK
Output hold time, from sample
edge of SCLK to MOSI data update
Input setup time, from MISO data Tds_mi
valid to sample edge of SCLK
Input hold time, from sample
edge of SCLK to MISO data update
Time from CS assert to first SCLK
edge
Time from first SCLK edge to CS
deassert
Tdh_mo
–
63
TBD
TBD
–
–
Tdh_mi
Tsu_cs
Thd_cs
–
c
c
½ SCLK period – 1
½ SCLK period
5
6
–
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled.
BROADCOM
®
September 9, 2013 • 20730-DS108-R
Page 49
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