PRELIMINARY
CYW20713
5.2 HCI Transport Detection Configuration
The CYW20713 supports the following interface types for the HCI transport from the host:
■ UART (H4 and H5)
■ SPI
Only one host interface can be active at a time. The firmware performs a transport detect function at boot-time to determine which
host is the active transport. It can auto-detect the UART interface, but the SPI interface must be selected by strapping the SCL pin to 0.
The complete algorithm is summarized as follows:
1. Determine if SCL is pulled low. If it is, select SPI as HCI host transport.
2. Determine if any local NVRAM contains a valid configuration file. If it does and a transport configuration entry is
present, select the active transport according to entry, and then exit the transport detection routine.
3. Look for CTS_N = 0 on the UART interface. If it is present, select UART.
4. Repeat Step 3 until transport is determined.
5.3 UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, CTS) with adjustable baud rates from 9600 bps to 4.0
Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud
rate can be selected via a vendor-specific UART HCI command. The interface supports Bluetooth UART HCI (H4) specifications. The
default baud rate for H4 is 115.2 Kbaud.
The following baud rates are supported:
■ 9600
■ 115200
■ 230400
■ 460800
■ 921600
■ 1444444
■ 1500000
■ 2000000
■ 3000000
■ 3250000
■ 3692000
■ 4000000
■ 14400
■ 19200
■ 28800
■ 38400
■ 57600
Normally, the UART baud rate is set by a configuration record downloaded after reset or by automatic baud rate detection. The host
does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is provided through a
vendor-specific command.
The CYW20713 UART operates with the host UART correctly, provided the combined baud rate error of the two devices is within ±2%.
5.3.1 HCI 3-Wire Transport (UART H5)
The CYW20713 supports H5 UART transport for serial UART communications. H5 reduces the number of signal lines required by
eliminating CTS and RTS, when compared to H4. In addition, in-band sleep signaling is supported over the same interface so that
the 4-wire UART and the 2-wire sleep signaling interface can be reduced to a 2-wire UART interface, saving four I/Os on the host.
H5 requires the use of an external LPO. CTS must be pulled low.
5.4 SPI
The CYW20713 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible.
The physical interface between the SPI master and the CYW20713 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI, and
SPI_SO) and one interrupt signal (SPI_INT). The CYW20713 can be configured to accept active-low or active-high polarity on the
SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on
the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, half-
duplex handshaking is implemented between the SPI master and the CYW20713.
SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload.
The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it
controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols.
Document Number: 002-14806 Rev. *C
Page 19 of 52
CYPRESS [ CYPRESS ]
