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BCM20706UA1KFFB4G 参数 Datasheet PDF下载

BCM20706UA1KFFB4G图片预览
型号: BCM20706UA1KFFB4G
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, CMOS, PBGA49, 4.50 X 4 MM, ROHS COMPLIANT, FBGA-49]
分类和应用: 电信电信集成电路
文件页数/大小: 58 页 / 1297 K
品牌: CYPRESS [ CYPRESS ]
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BCM20706 Data Sheet  
PCM Interface  
Slot Mapping  
The BCM20706 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM  
interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting  
scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of  
slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number  
of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO  
channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to  
allow other devices to share the same PCM interface signals. The data output driver tristates its output after the  
falling edge of the PCM clock during the last bit of the slot.  
Frame Synchronization  
The BCM20706 supports both short- and long-frame synchronization in both master and slave modes. In short-  
frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate  
that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks  
for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge  
of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse  
at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first  
bit of the first slot.  
Data Formatting  
The BCM20706 may be configured to generate and accept several different data formats. For conventional  
narrowband speech mode, the BCM20706 uses 13 of the 16 bits in each PCM frame. The location and order of  
these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits  
are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The  
default format is 13-bit 2’s complement data, left justified, and clocked MSB first.  
Burst PCM Mode  
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty  
cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to  
24 MHz. This mode of operation is initiated with an HCI command from the host.  
Broadcom®  
Bluetooth SoC  
May 19, 2016 • 20706-DS202-R  
Page 18  
BROADCOM CONFIDENTIAL  
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