CYW20704
5. Peripheral Transport Unit
This section discusses the PCM, USB, UART, I2S, and SPI peripheral interfaces. The CYW20704 has a 1040-byte transmit and
receive FIFO, which is large enough to hold the entire payload of the largest EDR BT packet (3-DH5).
5.1 PCM Interface
The CYW20704 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the
CYW20704 can connect to linear PCM Codec devices in master or slave mode. In master mode, the CYW20704 generates the
PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are
inputs to the CYW20704.
The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.
5.1.1 Slot Mapping
The CYW20704 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sam-
ple interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz,
or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to
allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the
PCM clock during the last bit of the slot.
5.1.2 Frame Synchronization
The CYW20704 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchroniza-
tion mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization sig-
nal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
5.1.3 Data Formatting
The CYW20704 may be configured to generate and accept several different data formats. For conventional narrowband speech
mode, the CYW20704 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to sup-
port various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a
sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
5.1.4 Wideband Speech Support
When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM
bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-
bit samples, resulting in a 64 Kbps bit rate. The CYW20704 also supports slave transparent mode using a proprietary rate-matching
scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 Kbps rate) is transferred over the PCM bus.
Document Number: 002-14786 Rev. *E
Page 15 of 49
CYPRESS [ CYPRESS ]
