B9949
Pin Description [1]
Pin
Name
PWR
I/O
I, PD
I, PU
I, PU
O
Description
6
PECL_CLK
PECL_CLK#
TCLK(0,1)
QA(1,0)
PECL Input Clock.
PECL Input Clock.
7
4, 5
External Reference/Test Clock Input.
Clock Outputs.
49, 51
VDDC
VDDC
VDDC
VDDC
42, 44, 46
31, 33, 35, 37
QB(2:0)
O
Clock Outputs.
QC(3:0)
O
Clock Outputs.
16, 18, 20, 22,
24, 28
QD(5:0)
O
Clock Outputs.
9, 10, 11, 12
DSEL(A:D)
TCLK_SEL
PCLK_SEL
MR_OE#
I, PD
I, PD
I, PD
I, PD
Divider Select Inputs. When HIGH, selects ÷2 input divider. When
LOW, selects ÷1 input divider.
2
TCLKSelect Input. WhenLOW, TCLK0clockis selectedandwhen
HIGH TCLK1 is selected.
PECL Select Input. When HIGH, PECL clock is selected and when
LOW TCLK(0,1) is selected
8
1
Output Enable Input. When asserted LOW, the outputs are en-
abled and when asserted HIGH, internal flip-flops are reset and
the outputs are three-stated.
17, 21, 25, 32,
36, 41, 45, 50
VDDC
3.3V Power Supply for Output Clock Buffers.
3
VDD
VSS
3.3V Power Supply
Common Ground
13, 15, 19, 23,
29, 30, 34, 38,
43, 47, 48, 52
14, 26, 27, 39,
40,
NC
Not Connected
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-Up.
Document #: 38-07081 Rev. *C
Page 3 of 8
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