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B9948LAA 参数 Datasheet PDF下载

B9948LAA图片预览
型号: B9948LAA
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V / 3.3V , 160 MHz时,一点12分时钟分配缓冲区 [2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer]
分类和应用: 时钟驱动器逻辑集成电路输出元件
文件页数/大小: 6 页 / 65 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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B9948L
AC Parameters
[6]
:
V
DDC
= 2.5V±5% or 3.3V ±5%, V
DD
= 3.3V ±5%, T
A
= –40°C to +85°C
Parameter
Fmax
Tpd
Description
Maximum Input Frequency
[7]
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
[7]
FoutDC
tpZL, tpZH
tpLZ, tpHZ
Tskew
Tskew (pp)
Output Duty Cycle
[7,8]
Output enable time (all outputs)
Output disable time (all outputs)
Output-to-Output Skew
[7,9]
Part to Part Skew
[10]
Set-up Time
[7,11]
Hold Time
[7,11]
Output Clocks Rise/Fall Time
[9]
PECL_CLK to Q
TCLK to Q
Ts
SYNC_OE to PECL_CLK
SYNC_OE to TCLK
Th
PECL_CLK to SYNC_OE
TCLK to SYNC_OE
Tr/Tf
10% to 90%
1.0
0.0
0.0
1.0
0.3
1.6
ns
ns
1.5
2.0
ns
Measured at VDDC/2
Conditions
Min.
160
4.0
4.4
TCYCLE/2 –
1000
2
2
-
-
9.0
8.9
TCYCLE/2 +
1000
10
10
200
ps
ns
ns
ps
ns
Typ.
Max.
Unit
MHz
ns
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7.
Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. Outputs loaded with 30 pF each
10. Part-to-Part Skew at a given temperature and voltage.
11. Set-up and Hold times are relative to the falling edge of the input clock
Ordering Information
Part Number
[12]
B9948LAA
Package Type
32-Pin TQFP
Industrial, –40°C to +85°C
Production Flow
Note:
12. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below.
Marking: Example:
Cypress
B9948LAA
Date Code, Lot #
B9948LAA
Package
A = TQFP
Revision
Device Number
Document #: 38-07080 Rev. *C
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