B9946
Pin Description
[1]
Pin
3, 4
26, 28, 30
19, 21, 23
10, 12, 14, 16
5, 6, 7
1
32
Name
TCLK(0,1)
QA(2:0)
QB(2:0)
QC(0:3)
DSEL(A:C)
TCLK_SEL
MR/OE#
VDDC
VDDC
VDDC
PWR
I/O
I, PU
O
O
O
I, PD
I, PD
I, PD
Clock Outputs
Clock Outputs
Clock Outputs
Divider Select Inputs. When HIGH, selects
÷2
input divider. When
LOW, selects
÷1
input divider.
TCLK Select Input. When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
Output Enable Input. When asserted LOW, the outputs are enabled
and when asserted HIGH, internal flip-flops are reset and the out-
puts are three-stated.
3.3V Power Supply for Output Clock Buffers
3.3V Power Supply
Common Ground
Description
External Reference/Test Clock Input
9, 13, 17, 18, 22,
25, 29
2
8, 11, 15, 20, 24,
27, 31
VDDC
VDD
VSS
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-Up.
Document #: 38-07077 Rev. *C
Page 2 of 5
CYPRESS [ CYPRESS SEMICONDUCTOR ]
