B9940L
Pin Description
[1]
Pin
5
6
3
Name
PECL_CLK
PECL_CLK#
TCLK
VDDC
PWR
I/O
I, PU
PECL Input Clock
I, PD
PECL Input Clock
I, PD
External Reference/Test Clock Input
O
Clock Outputs
Description
9, 10, 11, 13, Q(17:0)
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
4
8, 16, 29
7, 21
TCLK_SEL
VDDC
VDD
I, PD
Clock Select Input.
When LOW, PECL clock is selected and when
HIGH TCLK is selected.
3.3V or 2.5V Power Supply for Output Clock Buffers
3.3V or 2.5V Power Supply
Common Ground
1, 2, 12, 17, 25 VSS
Note:
1. PD = internal pull-down, PU = internal pull-up.
Document #: 38-07105 Rev. *C
Page 2 of 5