B9846
2-DIMM DDR Clock Distribution Buffer/Driver
Features
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Supports 266 MHz DDR SDRAM
Supports VIA Pro 266, PM266, and KT266 chipsets
Operating frequency: 60 MHz – 170 MHz
6 differential pairs
Spread-spectrum-compatible
Low jitter (cycle-to-cycle): < 75 ps
Very low skew: < 100 ps
Fast propagation delay: < 4.5nS
50% duty cycle
Power management via I
2
C interface
2.5V power supply
28-pin SSOP
Description
The B9846 is a high performance, low-skew, low jitter buffer
designed to distribute differential clocks in high-speed applica-
tions. The B9846 generates six differential pair clock outputs
to support two DDR Dimms. In addition, the B9846 features a
feedback clock output, FBOUT. This output is for the chipset
or other B9846 devices and/or one of Cypress’s zero-delay
buffers. Typically, The B9846 is used with C9846 clock synthe-
sizer for the VIA Pro 266 chipset, and with the C9854 clock
synthesizer for the VIA KT266 chipset.
The I
2
C interface enables/disables differential pair outputs.
This feature allows flexibility in system power management.
Block Diagram
FBOUT
BUFIN
DDRT0
DDRC0
DDRT1
DDRC1
SCLK
SDATA
Pin Configuration
FBOUT
VSS
DDRT0
DDRC0
VDD2.5V
VSS
DDRT1
DDRC1
VDD2.5V
BUFIN
VSS
DDRT2
DDRC2
VDD2.5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DDRT5
DDRC5
VDD2.5V
VSS
DDRT4
DDRC4
VDD2.5V
VSS
DDRT3
DDRC3
VDD2.5V
SCLK
SDATA
Control
Logic
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
Cypress Semiconductor Corporation
Document #: 38-07299 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised December 22, 2002
CYPRESS [ CYPRESS SEMICONDUCTOR ]
