The internal block at 0x7B40-0x7FFF (labeled “Registers”) contains the bulk buffer mem-
ory and EZ-USB control registers. As previously mentioned, they are aliased at 0x1B40-
0x1FFF to allow adding unused bulk buffer RAM to general-purpose memory. 8051 code
should access this memory only at the 0x7B40-0x7BFF addresses. External RAM may be
added from 0x0000 to 0xFFFF, but the regions shown by Note 1 in Figure 3-4 are ignored;
no external strobes or select signals are generated when the 8051 executes a MOVX
instruction that addresses these regions.
3.4
CS# and OE# Signals
The EZ-USB core automatically gates the standard 8051 RD# and WR# signals to exclude
selection of external memory that exists internal to the EZ-USB part. The PSEN# signal is
also available on a pin for connection to external code memory.
Some 8051 systems implement external memory that is used as both data and program
memory. These systems must logically OR the PSEN# and RD# signals to qualify the
chip enable and output enable signals of the external memory. To save this logic, the EZ-
USB core provides two additional control signals, CS# and OE#. The equations for these
signals are as follows:
•
•
CS# = RD# or WR# or PSEN#
OE# = RD# or PSEN#
Because the RD#, WR#, and PSEN# signals are already qualified by the addresses allo-
cated to external memory, these strobes are active only when external memory is accessed.
EZ-USB TRM v1.9
Chapter 3. EZ-USB Memory
Page 3-5
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