2 EZ-USB CPU
2.1
Introduction
The EZ-USB built-in microprocessor, an enhanced 8051 core, is fully described in Appen-
dices A-C. This chapter introduces the processor, its interface to the EZ-USB core, and
describes architectural differences from a standard 8051.
2.2
8051 Enhancements
The enhanced 8051 core uses the standard 8051 instruction set. Instructions execute faster
than with the standard 8051 due to two features:
•
Wasted bus cycles are eliminated. A bus cycle uses four clocks, as compared to 12
clocks with the standard 8051.
•
The 8051 runs at 24 MHz.
In addition to the speed improvement, the enhanced 8051 core also includes architectural
enhancements:
1. A second data pointer.
2. A second UART.
3. A third, 16-bit timer (TIMER2).
4. A high-speed memory interface with a non-multiplexed 16-bit address bus.
5. Eight additional interrupts (INT2-INT5, PFI, T2, and UART1).
6. Variable MOVX timing to accommodate fast/slow RAM peripherals.
7. 3.3V operation.
EZ-USB TRM v1.9
Chapter 2. EZ-USB CPU
Page 2-1
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