48-pin Variants
There are two 48-pin devices:
AN2122T
AN2126T
The four extra pins are used as follows:
•
PA7, PA6, and PA0 are GPIO pins. This makes five of the eight PORTA pins
available (all except PA1-PA3).
•
CPU12MHZ - This input controls the speed of the 8051:
-
-
tied high 12 MHz
tied low 24 MHz
Bulk Endpoints
The AN2122 and AN2126 have a reduced set of thirteen bulk endpoints (see Section 6.1,
"Introduction").
Interrupts
The AN2122 and AN2126 contain two interrupts not present in the other AN21xx family
members.
•
An IBN (In-Bulk NAK) interrupt request activates when an IN packet is NAKd by
the SIE because the 8051 has not loaded the buffer (and byte count register) for an
IN endpoint. This is useful for applications that need to know when the host is
pinging an IN endpoint (see Section 9.13, "In Bulk NAK Interrupt - (AN2122/
AN2126 only)").
•
An I2C interrupt source is added to the I2C interrupt (INT3), indicating that trans-
mission of a STOP bit is complete (see Section 9.14, "I2C STOP Complete Inter-
rupt - (AN2122/AN2126 only)").
1.19 Revision ID
The Revision ID for each part is shown in Table 1.2. The revision value is reported in the
internal DID (Device ID), which is the value read by the host during enumeration if no
EEPROM is connected to the I2C bus. This value also appears in the CPUCS register bits.
EZ-USB TRM v1.9
Chapter 1. Introducing EZ-USB
Page 1-17
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