A.3
Performance Overview
The 8051 core has been designed to offer increased performance by executing instructions in a
4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard 8051 (see Figure A-1.).
The shortened bus timing improves the instruction execution rate for most instructions by a
factor of three over the standard 8051 architectures.
Some instructions require a different number of instruction cycles on the 8051 core than they
do on the standard 8051. In the standard 8051, all instructions except for MULand DIVtake
one or two instruction cycles to complete. In the 8051 core, instructions can take between one
and five instruction cycles to complete. The average speed improvement for the entire
instruction set is approximately 2.5X, calculated as follows:
Number of Opcodes
Speed Improvement
150
3.0X
1.5X
51
43
2
2.0X
2.4X
Total: 255
Average: 2.5X
Note: Comparison is for 8051 and standard 8051
running at the same clock frequency.
A - 2
Appendix A: 8051 Introduction
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