Figure 12-1. Register Description Format ............................................................................ 12-2
Figure 12-2. Bulk Data Buffers ............................................................................................ 12-3
Figure 12-3. Isochronous Data FIFOs .................................................................................. 12-4
Figure 12-4. Isochronous Byte Counts ................................................................................. 12-6
Figure 12-5. CPU Control and Status Register ..................................................................... 12-8
Figure 12-6. IO Port Configuration Registers ...................................................................... 12-9
Figure 12-7. Output Port Configuration Registers ............................................................. 12-11
Figure 12-8. PINSn Registers ............................................................................................. 12-12
Figure 12-9. Output Enable Registers ................................................................................ 12-13
Figure 12-10. 230-Kbaud UART Operation Register .......................................................... 12-14
Figure 12-11. Isochronous OUT Endpoint Error Register ................................................... 12-14
Figure 12-12. Isochronous Control Register ........................................................................ 12-15
Figure 12-13. Zero Byte Count Register .............................................................................. 12-15
Figure 12-14. I2C Transfer Registers .................................................................................... 12-16
Figure 12-15. I2C Mode Register ......................................................................................... 12-18
Figure 12-16. Interrupt Vector Register ............................................................................... 12-19
Figure 12-17. IN/OUT Interrupt Request (IRQ) Registers ................................................... 12-20
Figure 12-18. USB Interrupt Request (IRQ) Registers ........................................................ 12-21
Figure 12-19. IN/OUT Interrupt Enable Registers ............................................................... 12-23
Figure 12-20. USB Interrupt Enable Register ...................................................................... 12-24
Figure 12-21. Breakpoint and Autovector Register .............................................................. 12-26
Figure 12-22. IN Bulk NAK Interrupt Request Register ...................................................... 12-27
Figure 12-23. IN Bulk NAK Interrupt Enable Register ....................................................... 12-27
Figure 12-24. IN/OUT Interrupt Enable Registers ............................................................... 12-28
Figure 12-25. Port Configuration Registers ......................................................................... 12-29
Figure 12-26. IN Control and Status Registers ..................................................................... 12-32
Figure 12-27. IN Byte Count Registers ................................................................................ 12-34
Figure 12-28. OUT Control and Status Registers ................................................................. 12-35
Figure 12-29. OUT Byte Count Registers ............................................................................ 12-36
Figure 12-30. Setup Data Pointer High/Low Registers ........................................................ 12-37
Figure 12-31. USB Control and Status Registers ................................................................. 12-38
Figure 12-32. Data Toggle Control Register ........................................................................ 12-40
Figure 12-33. USB Frame Count High/Low Registers ........................................................ 12-41
Figure 12-34. Function Address Register ............................................................................. 12-42
Figure 12-35. USB Endpoint Pairing Register ..................................................................... 12-43
Figure 12-36. IN/OUT Valid Bits Register .......................................................................... 12-44
Figure 12-37. Isochronous IN/OUT Endpoint Valid Bits Register ...................................... 12-45
Figure 12-38. Fast Transfer Control Register ....................................................................... 12-46
Figure 12-39. Auto Pointer Registers ................................................................................... 12-48
Figure 12-40. SETUP Data Buffer ....................................................................................... 12-49
Figure 12-41. SETUP Data Buffer ....................................................................................... 12-50
Figure 13-1. External Memory Timing ................................................................................ 13-4
Figure 13-2. Program Memory Read Timing ....................................................................... 13-4
Figure 13-3. Data Memory Read Timing ............................................................................. 13-5
Figure 13-4. Data Memory Write Timing ............................................................................ 13-5
EZ-USB TRM v1.9
List of Figures
ix
CYPRESS [ CYPRESS ]
