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AN2131QC 参数 Datasheet PDF下载

AN2131QC图片预览
型号: AN2131QC
PDF下载: 下载PDF文件 查看货源
内容描述: 在EZ - USBTM集成电路 [The EZ-USBTM Integrated Circuit]
分类和应用:
文件页数/大小: 334 页 / 1468 K
品牌: CYPRESS [ CYPRESS ]
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As shown in Table 5-2, after enumeration, the EZ-USB core responds to the following  
host requests.  
Set or clear an endpoint stall (Set/Clear Feature-Endpoint).  
Read the stall status for an endpoint (Get_Status_Endpoint).  
Set/Read an 8-bit configuration number (Set/Get_Configuration).  
Set/Read a 2-bit interface alternate setting (Set/Get_Interface).  
Download or upload 8051 RAM.  
To ensure proper operation of the default Keil Monitor, which uses SIO-1 (RXD1 and  
TXD1), never change the following Port Config bits from “1”:  
PORTBCFG bits 2 (RXD1) and 3 (TXD1).  
To ensure the 8051 processor can access the external SRAM (including the Keil Monitor),  
do not change the following bits from “1”:  
PORTCCFG bits 6 (WR#) and 7 (RD#).  
To ensure that no bits are unintentionally changed, all writes to the PORTxCFG registers  
should use a read-modify-write series of instructions.  
5.4  
Firmware Load  
The USB Specification provides for vendor-specific requests to be sent over CONTROL  
endpoint zero. The EZ-USB chip uses this feature to transfer data between the host and  
EZ-USB RAM. The EZ-USB core responds to two “Firmware Load” requests, as shown  
in Tables 5-3 and 5-4.  
Table 5-3. Firmware Download  
Byte  
0
Field  
Value  
0x40  
Meaning  
8051 Response  
bmRequest  
bRequest  
wValueL  
wValueH  
wIndexL  
wIndexH  
wLenghtL  
wLengthH  
Vendor Request, OUT None required  
1
0xA0 Firmware Load”  
2
AddrL Starting Address  
3
AddrH  
4
0x00  
5
0x00  
6
LenL Number of Bytes  
7
LenH  
EZ-USB TRM v1.9  
Chapter 5. EZ-USB CPU  
Page 5-5  
 
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