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AN2131QC 参数 Datasheet PDF下载

AN2131QC图片预览
型号: AN2131QC
PDF下载: 下载PDF文件 查看货源
内容描述: 在EZ - USBTM集成电路 [The EZ-USBTM Integrated Circuit]
分类和应用:
文件页数/大小: 334 页 / 1468 K
品牌: CYPRESS [ CYPRESS ]
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function  
2125S  
2126S  
2135S  
2136S  
2121S  
2131Q 2122S  
2131S  
2122T 2126T  
Name  
Type Default  
Description  
21  
18  
1
10  
7
10  
11  
7
11  
7
AVCC  
AGND  
Power  
Power  
N/A Analog Vcc. This signal provides power to the ana-  
log section of the chip.  
7
N/A Analog Ground. Connect to ground with as short a  
path as possible.  
43  
43  
47  
47  
DISCON# Output  
HI  
Disconnect. This pin is controlled by two bits,  
DISCOE and DISCON. When DISCOE=0, the pin  
floats. When DISCOE=1, it drives. When  
DISCOE=1, the driven logic level is the inverse of  
the DISCON bit.  
77  
79  
41  
42  
41  
42  
45  
46  
45  
46  
USBD  
USBD  
I/O/Z  
I/O/Z  
Z
Z
USB D- signal. Connect to the USB D- signal  
through a 24-ohm resistor.  
USB D+ signal. Connect to the USB D+ pin through  
a 24-ohm resistor.  
7-12,  
15,16,  
26-29,  
34-37  
N/A  
N/A  
N/A  
N/A  
A0-A5, A6, Output 0x0000 8051 Address bus. This bus is driven at all times.  
A7, A8-A11,  
A12-A15  
When the 8051 is addressing internal RAM it reflects  
the internal address.  
48-51, N/A 24-27, N/A 26-29, D0-D3, D4- I/O/Z  
Z
8051 Data bus. This bi-directional bus is high-  
impedance when inactive, input for bus reads, and  
output for bus writes. The data bus is also used to  
transfer data directly to and from internal EZ-USB  
FIFOs under control of the FRD# and FWR#  
strobes. D0-D7 are active only for external bus  
accesses, and are driven low in suspend.  
57-60  
28-31  
30-33  
D7  
80  
61  
N/A  
32  
N/A  
32  
N/A  
35  
N/A  
35  
PSEN#  
BKPT  
Output  
Output  
H
0
Program Store Enable. This active-low signal indi-  
cates a code fetch from external memory. It is active  
for program memory fetches above 0x1B40 when  
the EA pin is LO, or above 0x0000 when the EA  
pin is HI.  
Breakpoint. This pin goes active (high) when the  
8051 address bus matches the BPADDRH/L regis-  
ters and breakpoints are enabled in the USBBAV  
register (BPEN=1). If the BPPULSE bit in the  
USBBAV register is HI, this signal pulses high for  
eight 24-MHz clocks. If the BPPULSE bit is LO, the  
signal remains high until the 8051 clears the BREAK  
bit (by writing 1 to it) in the USBBAV register.  
25  
13  
13  
14  
14  
RESET  
Input  
N/A Active High Reset. Resets the 8051 and the USB  
SIE. This pin is normally tied to ground through a  
10K-ohm resistor and to Vcc through a 1 µF capac-  
itor.  
EZ-USB TRM v1.9  
Chapter 1. Introducing EZ-USB  
Page 1-23  
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