C.3.6 Multiprocessor Communications
The multiprocessor communication feature is enabled in modes 2 and 3 when the SM2 bit is
set in the SCON SFR for a serial port (SM2_0 for Serial Port 0, SM2_1 for Serial Port 1). In
multiprocessor communication mode, the 9th bit received is stored in RB8_0 (or RB8_1) and,
after the stop bit is received, the serial port interrupt is activated only if RB8_0 (or RB8_1) =
1.
A typical use for the multiprocessor communication feature is when a master wants to send a
block of data to one of several slaves. The master first transmits an address byte that identifies
the target slave. When transmitting an address byte, the master sets the 9th bit to 1; for data
bytes, the 9th bit is 0.
With SM2_0 (or SM2_1) = 1, no slave will be interrupted by a data byte. However, an address
byte interrupts all slaves so that each slave can examine the received address byte to
determine whether that slave is being addressed. Address decoding must be done by software
during the interrupt service routine. The addressed slave clears its SM2_0 (or SM2_1) bit and
prepares to receive the data bytes. The slaves that are not being addressed leave the SM2_0 (or
SM2_1) bit set and ignore the incoming data bytes.
C.3.7 Interrupt SFRs
The following SFRs are associated with interrupt control:
•
•
•
•
•
•
IE - SFR A8h (Table C-12.)
IP - SFR B8h (Table C-13.)
EXIF - SFR 91h (Table C-14.)
EICON - SFR D8h (Table C-15.)
EIE - SFR E8h (Table C-16.)
EIP - SFR F8h (Table C-17.)
The IE and IP SFRs provide interrupt enable and priority control for the standard interrupt
unit, as with the standard 8051. Additionally, these SFRs provide control bits for the Serial
Port 1 interrupt. These bits (ES1 and PS1) are available only when the extended interrupt unit
is implemented (ext_intr=1). Otherwise, they are read as 0.
Bits ES0, ES1, ET2, PS0, PS1, and PT2 are present, but not used, when the corresponding
module is not implemented.
The EXIF, EICON, EIE and EIP registers provide flags, enable control, and priority control
for the optional extended interrupt unit.
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 27
CYPRESS [ CYPRESS ]
