All DPTR-related instructions use the currently selected data pointer. To switch the active
pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC
DPS). This requires only one instruction to switch from a source address to a destination
address, saving application code from having to save source and destination addresses when
doing a block move.
Using dual data pointers provides significantly increased efficiency when moving large blocks
of data.
The SFR locations related to the dual data pointers are:
82h
83h
84h
85h
86h
DPL0 DPTR0 low byte
DPH0 DPTR0 high byte
DPL1 DPTR1 low byte
DPH1 DPTR1 high byte
DPS
DPTR Select (Bit 0)
B.1.7 Special Function Registers
The Special Function Registers (SFRs) control several of the features of the 8051. Most of the
8051 core SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs
that control features that are not available in the standard 8051.
Table B-4. lists the 8051 core SFRs and indicates which SFRs are not included in the standard
8051 SFR space.
In Table B-5., SFR bit positions that contain a 0 or a 1 cannot be written to and, when read,
always return the value shown (0 or 1). SFR bit positions that contain “-” are available but not
used. Table B-5. lists the reset values for the SFRs.
The following SFRs are related to CPU operation and program execution:
81h
D0h
E0h
F0h
SP
Stack Pointer
PSW
ACC
B
Program Status Word ()
Accumulator Register
B Register
Table B-6. lists the functions of the bits in the PSW SFR. Detailed descriptions of the
remaining SFRs appear with the associated hardware descriptions in Appendix C of this
databook.
B - 12
Appendix B: 8051 Architectural Overview
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