By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory
access, the software must set the stretch value to zero. The stretch value affects only data
memory access (not program memory).
The stretch value affects the width of the read/write strobe and all related timing. Using a
higher stretch value results in a wider read/write strobe, which allows the memory or
peripheral more time to respond.
Table B-3. lists the data memory access speeds for stretch values zero through seven. MD2–0
are the three LSBs of the Clock Control Register (CKCON.2–0).
Table B-3. Data Memory Stretch Values
Read/Write
Strobe Width
(Clocks)
Memory
Cycles
Strobe Width
@ 24MHz
MD2
MD1
MD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
83.3 ns
166.7 ns
333.3 ns
500 ns
3 (default)
4
4
5
6
7
8
9
8
12
16
20
24
28
666.7 ns
833.3 ns
1000 ns
1166.7 ns
B.1.6 Dual Data Pointers
The 8051core employs dual data pointers to accelerate data memory block moves. The
standard 8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or
peripherals. The 8051 maintains the standard data pointer as DPTR0 at SFR locations 82h
(DPL0) and 83h (DPH0). It is not necessary to modify existing code to use DPTR0.
The 8051 core adds a second data pointer (DPTR1) at SFR locations 84h (DPL1) and 85h
(DPH1). The SEL bit in the DPTR Select register, DPS (SFR 86h), selects the active pointer.
When SEL = 0, instructions that use the DPTR will use DPL0 and DPH0. When SEL = 1,
instructions that use the DPTR will use DPL1 and DPH1. SEL is the bit 0 of SFR location
86h. No other bits of SFR location 86h are used.
EZ-USB v1.9
Appendix B: 8051 Architectural Overview
B - 11
CYPRESS [ CYPRESS ]
