Table B-2. 8051 Instruction Set
Instr.
Cycles
Hex
Code
Mnemonic
Description
Byte
XCH A, @Ri
XCHD A, @Ri
Exchange A and data memory
Exchange A and data memory nibble
1
1
1
1
C6-C7
D6-D7
* Number of cycles is user-selectable. See “Stretch Memory Cycles (Wait States)” on page B-10.
Boolean
CLR C
Clear carry
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
2
2
2
C3
C2
D3
D2
B3
B2
82
CLR bit
Clear direct bit
SETB C
Set carry
SETB bit
CPL C
Set direct bit
Complement carry
Complement direct bit
AND direct bit to carry
AND direct bit inverse to carry
OR direct bit to carry
OR direct bit inverse to carry
Move direct bit to carry
Move carry to direct bit
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
B0
72
A0
A2
92
Branching
ACALL addr 11
LCALL addr 16
RET
Absolute call to subroutine
Long call to subroutine
Return from subroutine
Return from interrupt
2
3
1
1
2
3
2
2
2
3
3
4
4
4
3
4
3
3
3
4
11-F1
12
22
RETI
32
AJMP addr 11
LJMP addr 16
SJMP rel
Absolute jump unconditional
Long jump unconditional
Short jump (relative address)
Jump on carry = 1
01-E1
02
80
JC rel
40
JNC rel
Jump on carry = 0
50
JB bit, rel
Jump on direct bit = 1
20
B - 8
Appendix B: 8051 Architectural Overview
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