Table B-2. 8051 Instruction Set
Description
Instr.
Cycles
Hex
Code
Mnemonic
Byte
Logical
ANL, Rn
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
58-5F
55
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
AND direct byte to A
AND data memory to A
AND immediate to A
56-57
54
AND A to direct byte
52
AND immediate data to direct byte
OR register to A
53
48-4F
45
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XORL A, Rn
XORL A, direct
XORL A, @Ri
XORL A, #data
XORL direct, A
XORL direct, #data
CLR A
OR direct byte to A
OR data memory to A
OR immediate to A
46-47
44
OR A to direct byte
42
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR data memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate data to direct byte
Clear A
43
68-6F
65
66-67
64
62
63
E4
CPL A
Complement A
F4
SWAP A
Swap nibbles of a
C4
RL A
Rotate A left
23
RLC A
Rotate A left through carry
Rotate A right
33
RRA
03
RRC A
Rotate A right through carry
13
B - 6
Appendix B: 8051 Architectural Overview
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