B.1.2 Instruction Set
All 8051 instructions are binary code compatible and perform the same functions as they do
with the industry standard 8051. The effects of these instructions on bits, flags, and other
status functions is identical to the industry standard 8051. However, the timing of the
instructions is different, both in terms of number of clock cycles per instruction cycle and
timing within the instruction cycle.
Figure B-2 lists the 8051 instruction set and the number of instruction cycles required to
complete each instruction. Table B-1. defines the symbols and mnemonics used in Table B-2.
Lower 128 bytes
Indirect addressing only
7Fh
FFh
FFh
Direct RAM
Upper 128
bytes
SFR space
(optional)
30h
2Fh
. . .
7F
.
78
00
Bank
80h
7Fh
Select
(PSW bits
4,3)
80h
Bit-Addressable
.
Registers
.
Direct addressing only
Lower 128
bytes
. . .
07
20h
1Fh
18h
17h
Bank 3
11
10
01
00
00h
Bank 2
Bank 1
10h
0Fh
08h
07h
Direct or indirect addressing
Bank 0
00h
Figure B-2 Internal RAM Organization
EZ-USB v1.9
Appendix B: 8051 Architectural Overview
B - 3
CYPRESS [ CYPRESS ]
