Appendix B: 8051 Architectural Overview
B.1
Introduction
This appendix provides a technical overview and description of the 8051 core architecture.
PC4/TO, PC5/T1
8051
PA0/t0_out,
PA1/t0_out
PB0/T2
8051_cpu
8051_timer2
8051_timer
8051_ram_128
PB1/t2ex
PB7/t2out
Timer 2
Timers 0 and 1
(80..FFh indirect)
8051_ram_128
(lower 128 Byte RAM)
(0..7Fh direct/indirect)
PC1/TxD0
PC0/rxd0in
PA6/rxd0out
8051_serial
8051_intr_0
Serial Port 0
or
8051_alu
8051_
8051_intr_1
Interrupt Unit
PB3/txd1
PB2/rxd1in
PA7/rxd1out
8051_serial
Serial Port 1
8051_control
main_regs
interrupts
8051_biu
port_control
A15-A0
D7 - D0
CLK24
8051_op_decoder
RESET#
Figure B-1. 8051 Block Diagram
EZ-USB TRM v1.9
Appendix B: 8051 Architectural Overview
B - 1
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