12.15 Fast Transfers
FASTXFR
Fast Transfer Control
7FE2
b7
b6
b5
b4
b3
b2
b1
b0
FISO
FBLK
RPOL
RMOD1
RMOD0
WPOL
WMOD1
WMOD0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Figure 12-38. Fast Transfer Control Register
The EZ-USB core provides a fast transfer mode that improves the8051 transfer speed
between external logic and the isochronous and bulk endpoint buffers. The FASTXFR
register enables the modes for bulk and/or isochronous transfers, and selects the timing
waveforms for the FRD# and FWR# signals.
Bit 7:
FISO
Enable Fast ISO Transfers
The 8051 sets FISO=1 to enable fast isochronous transfers for all16 isochronous endpoint
FIFOs. When FISO=0, fast transfers are disabled for all 16 isochronous endpoints.
Bit 6:
FBLK
Enable Fast BULK Transfers
The 8051 sets FBLK=1 to enable fast bulk transfers using the Autopointer (see Section
12.16, "SETUP Data") with BULK endpoints. When FBLK=0 fast transfers are disabled
for BULK endpoints.
Bit 5:
RPOL
FRD# Pulse Polarity
The 8051 sets RPOL=0 for active-low FRD# pulses, and RPOL=1 for active high FRD#
pulses.
Bit 4-3:
RMOD
FRD# Pulse Mode
These bits select the phasing and width of the FRD# pulse. See Figure 8-12.
Page 12-46
Chapter 12. EZ-USB Registers
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
