The IO bit selects the endpoint direction (1=IN, 0=OUT), and the EP2-EP1-EP0 bits select
the endpoint number. The Q bit, which is read-only, indicates the state of the data toggle
for the selected endpoint. Writing R=1 sets the data toggle to DATA0, and writing S=1
sets the data toggle to DATA1.
Note
At the present writing, there appears to be no reason to set a data toggle to DATA1. The
S bit is provided for generality.
To clear an endpoint’s data toggle, the 8051 performs the following sequence:
•
Select the endpoint by writing the value 000D0EEE to the TOGCTL register,
where D is the direction and EEE is the endpoint number.
•
Clear the toggle bit by writing the value 001D0EEE to the TOGCTL register.
After step 1, the 8051 may read the state of the data toggle by reading the TOGCTL regis-
ter checking bit 7.
Page 6-12
Chapter 6. EZ-USB CPU
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
